The present invention relates to a method of producing a self-aligned gate electrode of a field effect transistor, and more particularly, relates to a method of producing an insulating film pattern for forming a self-aligned gate electrode in the process of producing a field effect transistor.
Conventionally, substitutional and refractory metal techniques are used in forming gates in field effect transistors. The substitional technique is more flexible than the refractory metal approach since the gate material can be selected at will. However, such process has disadvantages as described below.
FIGS. 1(a)-1(i) illustrate a part of the typical conventional process of producing a Schottky-gate field effect transistor.
As shown in FIG. 1(a), a protective insulating film 12 such as a Si.sub.3 N.sub.4 film is formed on a semiconductor substrate 10, and then a three-layered resist composed of a resist 14, an insulating film 16 such as a SiO.sub.2 film, and another resist 18 is formed. The insulating film 16 is then etched while masked with a resist pattern 18A formed by patterning the uppermost resist 18 as shown in FIG. 1(b), to prepare an insulating film pattern 16A. Next, the resist 14 is etched by RIE while masked with the insulating film pattern 16A to thereby form a resist pattern 14A. While masked with the insulating film pattern 16A and the resist pattern 14A, ion implantation is carried out as shown by the arrow 20 of FIG. 1(c) to thereby form a source region 22A and a drain region 22B.
After the implantation of the source and drain regions, an SiO.sub.2 film 24 is formed on the surface of the substrate by sputtering or the like is shown in FIG. 1(d). After slight-etching, the resist pattern 14A and insulator 16A are removed by lift-off method to thereby form a reversal pattern 24A of the SiO.sub.2 film as shown in FIG. 1(e).
Further, as shown in FIG. 1(f), after ohmic electrodes 26A and 26B are respectively formed on the source region 22A and the drain region 22B, a three-layered resist 28 is formed again over the entire surface of the substrate.
Next, the uppermost layer of the three-layered resist 28 is patterned to have an opening corresponding to a gate electrode. The insulating film formed at the middle layer of the three-layered resist 28 is masked with the resulting resist pattern formed at the uppermost layer. Further, the lowermost layer of the three-layered resist 28 is selectively removed while masked with the resulting insulating film pattern to thereby form a two-layered resist pattern 28 as shown in FIG. 1(g).
While masked with the pattern of the two-layered resist 28, a part of the insulating film 12 is removed by reactive-ion etching to thereby obtain an insulating film 12 with an opening 30 as shown in FIG. 1(h). Further, gate electrode material is deposited while masked with the pattern of the two-layered resist 28, and then the pattern of the two-layered resist 28 is removed by lift-off to thereby form a gate electrode 32 as shown in FIG. 1(i).
In the conventional method, however, the gate region of the crystal surface is often damaged by ion radiation because the insulating film 12 in direct contact with the semiconductor substrate 10 is removed by reactive-ion etching. Further, contamination with impurities in the etching process and in the cleaning process after etching is a problem. A damaged and contaminated surface causes deterioration in the characteristics of the field effect transistor.
Further, although a field effect transistor having a gate electrode self-aligned to source and drain regions can be attained by the conventional producing process, a lot of steps are required.